Bus interfaces are used in numerous electronic devices and systems to communicate data from one device to another. For instance, a network interface card may include a bus interface that communicates data (e.g., parallel and/or serial data) with any number of other devices, such as a computer motherboard or system memory, for example. There are a wide range of bus interface protocols and corresponding bus interfaces (e.g., circuits and/or logic) that are implemented in accordance with those bus interface protocols. Some examples of such protocols include the Peripheral Component Interconnect (PCI) protocol, the PCI Express (PCIE) protocol, the Universal Serial Bus (USB) protocol, the HyperTransport protocol and the InfiniBand protocol, among numerous other protocols.
Such bus interfaces may include complex circuitry including hundreds of thousands of logic gates. In certain cases, it may be desirable, at times, to operate a bus interface in a low power mode where certain parts of the circuitry are disabled to conserve dynamic power consumption. When operating in a low power mode, a bus interface may, however, retain some functionality. For instance, a bus interface operating in a low power mode may continue to support management functions, such as power management functions.
As device geometries (e.g., transistor channel lengths) in advanced semiconductor manufacturing processes continue to shrink (e.g., to 90 nm and smaller), leakage current becomes a much larger component of the overall power consumption of circuits implemented using such processes. Further, as use of high speed serial interfaces increases, the speed at which the interface logic for such interfaces operates (e.g., clock speed) also increases. Accordingly, such interfaces are generally implemented using high speed, low voltage threshold (Vt) devices. These low Vt devices have higher leakage current than higher threshold devices, especially on advanced semiconductor processes. With such increases in leakage current, it may be difficult or impossible to meet power consumption specifications for low power operating modes for various bus interface protocols. For example, the PCIE protocol specifies a current limit of 375 mA in the low power mode. On some devices (e.g., those fabricated using advanced semiconductor processes), leakage current for a PCIE bus interface may be on the order of several hundred milliamps and may even exceed the 375 mA current limit without accounting for any dynamic current of the bus interface in the low power operating mode. The high amount of leakage current may, therefore, severally limit the amount of logic in a given device that can be powered during the low power operating mode to provide a user with desired low power operating mode functionality.
The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art may become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.